Data storage devices, such as read only memories (“ROMs”), typically store data in arrays of memory cells. Generally, a memory cell consists of a single transistor for each bit to be stored. The memory array is typically permanently programmed during the fabrication process. Thus, ROM memory devices are generally used to store data or code that will not be altered after the ROM memory device is manufactured. Non-volatile ROM memory devices, such as electrically erasable programmable ROMs (EEPROMs), are capable of maintaining stored information even in the absence of power.
ROM memory devices are often fabricated, for example, using Complementary Metal Oxide Semiconductor (CMOS) semiconductor fabrication technologies. As the size of ROM memory devices decrease, with improvements in integrated circuit fabrication technologies, the more narrow trace widths and shorter channel lengths of the ROM memory cell transistors can cause high leakage currents, referred to as transistor sub-threshold leakage current. In previous CMOS technologies, where trace widths were on the order 0.16 micrometers (μm) or more, transistor sub-threshold leakage current was much lower, even for relatively short channel length and narrow width devices. ROM memories fabricated using these prior CMOS technologies typically did not suffer from significant leakage problems.
With more advanced CMOS technologies having trace widths of 0.16 μm or less, however, the transistor sub-threshold leakage current becomes a significant problem. A number of techniques have been proposed or suggested for reducing transistor sub-threshold leakage current in CMOS transistors, including the use of relatively long channel length or relatively wider channel width cell transistors (or both). Such techniques, however, cause an undesirable increase in the physical size of the memory device, reduce the maximum frequency of operation and increase the active and standby currents. A need therefore exists for improved techniques for reducing leakage current in ROM devices.